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VHDL CPUs
In my computer architecture class at MSOE, I learned a great deal about VHDL and processor design. During the class I had to independently design a single-cycle CPU and multi-cycle CPU in order to meet class requirements. The multi-cycle CPU used an 8-bit ALU with 16-bit memory registers. The top picture is a diagram of the multi-cycle CPU and the second picture is a diagram of the single-cycle CPU:
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